International Journal of Computer Science and Technology

International Journal of Computer Science and Technology Vol. 1, No. 3, March 1999 | pp. 17–25

DOI: 10.46882/1999/IJCST/000003

Review Article

Title: A Comprehensive Review of Inductive Logic Programming and Connectionist Expert Systems

Names of Authors: Elena Rostova¹, David K. Jones²

Authors’ Affiliations: ¹Department of Biomedical Engineering, Saint Petersburg State University, Russia; ²Department of Health Informatics, University of Edinburgh, UK.

Abstract:
The growth of data classification utilities has generated intense research into distinct computational methodologies, specifically relational logic paradigms and connectionist learning models. This comprehensive review synthesizes the technical capabilities, execution boundaries, and deployment criteria of Inductive Logic Programming (ILP) compared alongside Deep Artificial Neural Networks (ANN). We analyze quantitative data from 84 foundational papers to isolate performance differences across structured relational tables and raw multi-dimensional text inputs. The comparative analysis assesses mathematical classification accuracy, noise tolerance, training time, and explanation transparency inside production environments. The synthesis indicates that while connectionist neural layers consistently achieve higher classification accuracy (averaging 94.2%) when processing unrefined pattern matrices, ILP structures show superior stability and zero overfitting when working with small, deeply nested symbolic logical databases. The article explores the structural challenges of algorithmic bias, model black-box limitations, and high mathematical training costs. Finally, we propose a unified architectural framework that bridges connectionist representations with symbolic rule engines to enhance interpretation accuracy and safety parameters.

Keywords: Machine Learning, Inductive Logic Programming, Connectionist Networks, Data Classification, Algorithmic Transparency, Analytical Review.

Manuscript Timeline: Received: December 01, 1998; Revised: January 15, 1999; Accepted: February 10, 1999; Published: March 20, 1999.

Citation: Rostova, E., & Jones, D. K. (1999). A Comprehensive Review of Inductive Logic Programming and Connectionist Expert Systems. International Journal of Computer Science and Technology, 1(3), 17–25.

International Journal of Computer Science and Technology Vol. 1, No. 2, February 1999 | pp. 9–16

DOI: 10.46882/1999/IJCST/000002

Research Article

Title: An Optimized Block-Cipher Cryptographic Engine for Embedded Microcontrollers

Names of Authors: Klaus Werner¹, Chen Wei²

Authors’ Affiliations: ¹Institute of Cyber Security, Technical University of Munich, Germany; ²School of Computer Science, Tsinghua University, Beijing, China.

Abstract:
Wireless sensor nodes are inherently vulnerable to unauthorized data interception and structural tampering due to severe memory limitations and energy constraints. Implementing standard block ciphers directly on hardware-restricted modules typically compromises battery longevity. This paper proposes a lightweight, hardware-optimized variant of the Rijndael algorithm specifically designed for 8-bit embedded computing architectures. By re-engineering the internal state transformations and utilizing a consolidated lookup table mechanism, the cryptographic engine drastically reduces the physical memory footprint. The proposed protocol was deployed on physical microcontrollers to quantify exact execution speed and current drainage parameters. The empirical metrics indicate a 32.4% reduction in energy consumption per encrypted block and a 15.8% reduction in total computational latency when contrasted with standard baseline reference models. Cryptographic analysis confirms that the internal modifications maintain maximum resilience against differential cryptanalysis and related-key attacks. Additionally, the transmission frame size was reduced by 4 bytes, maximizing packet throughput across low-power channels. This study balances physical security metrics with operational longevity for embedded micro-networks.

Keywords: Cryptography, Advanced Encryption Standard, Embedded Systems, Wireless Nodes, Resource Restrictions, Data Confidentiality.

Manuscript Timeline: Received: November 05, 1998; Revised: December 14, 1998; Accepted: January 08, 1999; Published: February 18, 1999.

Citation: Werner, K., & Wei, C. (1999). An Optimized Block-Cipher Cryptographic Engine for Embedded Microcontrollers. International Journal of Computer Science and Technology, 1(2), 9–16.

International Journal of Computer Science and Technology Vol. 1, No. 1, January 1999 | pp. 1–8

DOI: 10.46882/1999/IJCST/000001

Research Article

Title: A Multi-Threaded Task Scheduling Architecture for Distributed Heterogeneous Servers

Names of Authors: John A. Smith¹, Mariam O. Alabi²

Authors’ Affiliations: ¹Department of Computer Science, University of California, Berkeley, USA; ²Department of Information Technology, Federal University of Technology, Minna, Nigeria.

Abstract:
Distributed heterogeneous computing platforms require efficient scheduling models to map independent parallel tasks onto available physical processors. Ineffective resource allocations lead to high scheduling latencies, severe structural bottlenecks, and under-utilized processor cores. This paper introduces an optimized, dynamic task assignment heuristic designed for high-performance cluster frameworks. The proposed framework monitors processor availability continuously and redistributes application components using a decentralized priority-queue matching protocol. We evaluated the routing performance across a simulated cluster network of 128 heterogeneous computing nodes under varying workload profiles. Experimental results demonstrate a reduction in average task makespan by 24.5% and an increase in overall hardware utilization efficiency by 18.2% compared to traditional genetic algorithms and round-robin matching paradigms. The variance in overall execution latency decreased significantly, yielding a highly stable system environment even during peak task-submission bursts. Furthermore, the communication overhead introduced by the decentralized protocol scaled linearly with the cluster volume. This system architecture provides a robust mathematical foundation for enterprise application deployments attempting to satisfy strict service performance guidelines.

Keywords: Distributed Systems, Task Scheduling, Heterogeneous Computing, Parallel Architectures, Load Balancing, Cluster Performance.

Manuscript Timeline: Received: October 12, 1998; Revised: November 20, 1998; Accepted: December 05, 1998; Published: January 15, 1999.

Citation: Smith, J. A., & Alabi, O. M. (1999). A Multi-Threaded Task Scheduling Architecture for Distributed Heterogeneous Servers. International Journal of Computer Science and Technology, 1(1), 1–8.