International Journal of Computer Science and Technology

International Journal of Computer Science and Technology | Vol. 6, No. 8, August 2004 | pp. 57–64

DOI: 10.46882/2004/IJCST/000061

Article Type: Research Article

Title: Design and Testing of a Fault-Tolerant Distributed Shared Memory Protocol for Linux Clusters

Names of Authors: Sophie Dubois¹, Hans-Werner Schmidt²

Authors’ Affiliations: ¹Department of Applied Cryptography, ENS Paris, France; ²Fraunhofer Institute for Secure Information Technology, Darmstadt, Germany

Abstract: Distributed Shared Memory (DSM) models simplify parallel programming pipelines but are prone to complete cluster failure if any individual computing node goes offline. This study outlines a robust, page-based Software DSM protocol that incorporates an asynchronous checkpointing infrastructure to guarantee fault tolerance. The software architecture tracks page modification actions using a relaxed, lazy release consistency model, saving differential page updates to non-volatile local storage blocks. Fault recovery evaluations conducted on a 32-node Linux workstation grid showed that our protocol handles unexpected node terminations cleanly, restoring cluster processing state within 1.45 s of failure detection. The performance penalty introduced by the checkpointing code loop caused a negligible throughput drop of less than 2.8% under typical matrix factorization workloads, offering a secure environment for long-running industrial compute loops.

Keywords: Distributed Shared Memory, Fault Tolerance, Workstation Clusters, Checkpointing, Consistency Models

Manuscript Timeline: Received: May 14, 2004; Revised: June 22, 2004; Accepted: July 19, 2004; Published: August 15, 2004

Citation: Dubois, S., & Schmidt, H.-W. (2004). Design and Testing of a Fault-Tolerant Distributed Shared Memory Protocol for Linux Clusters. International Journal of Computer Science and Technology, 6(8), 57–64.

International Journal of Computer Science and Technology | Vol. 6, No. 7, July 2004 | pp. 49–56

DOI: 10.46882/2004/IJCST/000060

Article Type: Original Research Paper

Title: An Object-Oriented Framework for the Synthesis and Compilation of Synchronous Dataflow Graphs

Names of Authors: Samuel Kwesi¹, Amara Diallo²

Authors’ Affiliations: ¹Department of Computer Engineering, Kwame Nkrumah University of Science and Technology, Kumasi, Ghana; ²African Institute for Mathematical Sciences, Dakar, Senegal

Abstract: Implementing complex digital signal processing (DSP) logic on multi-core hardware matrices requires specialized code synthesis methodologies to avoid runtime deadlock states. This paper details an object-oriented compilation framework developed to parse, analyze, and optimize Synchronous Dataflow (SDF) graphs. The compiler leverages an automated topological mapping engine that extracts concurrency properties and constructs static, periodic schedules at compile time. This process completely removes scheduling execution demands from the target microcontroller. We tested the system by generating production-grade C source code for an array of multi-channel audio filter networks. The synthesized application achieved a 15.6% reduction in code size compared to standard commercial tool suites. Furthermore, internal memory buffer allocations were optimized, reducing memory space demands by 28.3% while maintaining real-time latency profiles of less than 1.2 ms per audio frame block.

Keywords: Synchronous Dataflow, Code Generation, DSP Compilers, Embedded Software, Object-Oriented Synthesis

Manuscript Timeline: Received: April 09, 2004; Revised: May 20, 2004; Accepted: June 15, 2004; Published: July 09, 2004

Citation: Kwesi, S., & Diallo, A. (2004). An Object-Oriented Framework for the Synthesis and Compilation of Synchronous Dataflow Graphs. International Journal of Computer Science and Technology, 6(7), 49–56.

International Journal of Computer Science and Technology | Vol. 6, No. 6, June 2004 | pp. 41–48

DOI: 10.46882/2004/IJCST/000059

Article Type: Research Article

Title: A Relational Content-Based Image Retrieval System Using Multi-Feature Fusion and Relevance Feedback

Names of Authors: David Miller¹, Zhengyang Liu²

Authors’ Affiliations: ¹Department of Data Science, New York University, New York, USA; ²Department of Computer Science, National University of Singapore, Singapore

Abstract: Querying unlabelled digital image repositories using keyword search configurations often returns noisy and inaccurate results due to the semantic gap problem. This paper presents a Content-Based Image Retrieval (CBIR) engine that incorporates multi-feature fusion alongside a dynamic relevance feedback loop. The framework extracts global color histograms, Gabor filter texture vectors, and Zernike moment shape indicators to construct an uncompressed index file. We design a user-guided interactive tracking routine that updates feature weight parameters on the fly using a modified vector space model. Evaluated on an open dataset containing 10,000 photographic entries, our CBIR layout scored a mean average precision (MAP) rating of 84.6%, outperforming standalone color index searches by a margin of 21.5%. The query execution duration requires less than 42 ms per search, confirming its usability for production-grade digital asset systems.

Keywords: Content-Based Image Retrieval, Feature Fusion, Relevance Feedback, Texture Analysis, Computer Vision

Manuscript Timeline: Received: March 04, 2004; Revised: April 15, 2004; Accepted: May 12, 2004; Published: June 03, 2004

Citation: Miller, D., & Liu, Z. (2004). A Relational Content-Based Image Retrieval System Using Multi-Feature Fusion and Relevance Feedback. International Journal of Computer Science and Technology, 6(6), 41–48.

International Journal of Computer Science and Technology | Vol. 6, No. 5, May 2004 | pp. 33–40

DOI: 10.46882/2004/IJCST/000058

Article Type: Original Research Paper

Title: Cross-Layer Design Optimization for Energy-Constrained Wireless Video Sensor Networks

Names of Authors: Liam O'Connor¹, Fatima Al-Suwaidi²

Authors’ Affiliations: ¹School of Computer Science, Trinity College Dublin, Ireland; ²Department of Electrical Engineering, United Arab Emirates University, Al Ain, UAE

Abstract: Capturing and transmitting digital video streams over wireless sensor networks introduces extreme power drains, severely limiting node operational lifetimes. This study outlines an integrated cross-layer design framework that coordinates parameters across the application, transport, and MAC layers simultaneously. The architecture uses an adaptive H.263 video encoder that changes quantization parameters based on real-time channel bit error rates and residual battery metrics. Network validation tests using an array of embedded CMOS sensor nodes showed that our cross-layer paradigm extends individual node operational lifetimes by 34.6% compared to decoupled, standard layer configurations. The structural peak signal-to-noise ratio (PSNR) of the received video streams remained above 32.4 dB under high channel interference conditions. This optimization minimizes packet drop penalties by 21.2%, offering a robust strategy for long-term remote surveillance networks.

Keywords: Wireless Video Sensor Networks, Cross-Layer Design, Energy Conservation, Adaptive Video Encoding, Network Lifetime

Manuscript Timeline: Received: February 11, 2004; Revised: March 29, 2004; Accepted: April 19, 2004; Published: May 10, 2004

Citation: O'Connor, L., & Al-Suwaidi, F. (2004). Cross-Layer Design Optimization for Energy-Constrained Wireless Video Sensor Networks. International Journal of Computer Science and Technology, 6(5), 33–40.

International Journal of Computer Science and Technology | Vol. 6, No. 4, April 2004 | pp. 25–32

DOI: 10.46882/2004/IJCST/000057

Article Type: Research Article

Title: A Cryptographic Authentication Protocol for Secure Handover in Next-Generation Cellular Networks

Names of Authors: Ahmed Al-Mansoor¹, Yuki Tanaka²

Authors’ Affiliations: ¹Department of Computer Science, King Saud University, Riyadh, Saudi Arabia; ²Graduate School of Information Science, Kyoto University, Japan

Abstract: Rapid mobility across heterogeneous wireless cellular access points exposes mobile users to hijacking and eavesdropping risks during active handover phases. This paper details a lightweight, secure handover authentication protocol utilizing symmetric elliptic curve cryptography primitives. The proposed framework establishes transient session keys between mobile stations and foreign base stations without requiring continuous validation queries back to the home location register. Our mathematical validation profile confirms that the protocol remains completely secure against replay attacks, man-in-the-middle interventions, and forward-key exposure vectors. Hardware implementation tests conducted on a 32-bit embedded processor showed that the entire authentication computation concludes in 14.5 ms. This represents an execution efficiency gain of 38% over traditional public-key infrastructures, effectively suppressing handover communication dropouts to less than 0.5% under high velocity test scenarios.

Keywords: Mobile Security, Handover Authentication, Elliptic Curve Cryptography, Cellular Networks, Key Management

Manuscript Timeline: Received: January 15, 2004; Revised: February 22, 2004; Accepted: March 15, 2004; Published: April 14, 2004

Citation: Al-Mansoor, A., & Tanaka, Y. (2004). A Cryptographic Authentication Protocol for Secure Handover in Next-Generation Cellular Networks. International Journal of Computer Science and Technology, 6(4), 25–32.

International Journal of Computer Science and Technology | Vol. 6, No. 3, March 2004 | pp. 17–24

DOI: 10.46882/2004/IJCST/000056

Article Type: Original Research Paper

Title: A Specialized Genetic Algorithm for the Multi-Objective Structural Optimization of VLSI Floorplanning

Names of Authors: Elena Rostova¹, Carlos Mendez²

Authors’ Affiliations: ¹Faculty of Mathematics and Computer Science, Saint Petersburg State University, Russia; ²Department of Informatics, University of Barcelona, Spain

Abstract: As Very Large Scale Integration (VLSI) designs scale down to sub-micron process geometries, floorplanning becomes a dominant factor in determining overall chip performance, thermal boundaries, and manufacturing yield. This paper develops a multi-objective Genetic Algorithm (GA) optimized to solve the NP-hard floorplanning puzzle by minimizing total silicon area and wirelength simultaneously. We utilize a normalized bounded slicing tree representation to map layout coordinates, introducing a localized mutation operator that avoids premature population convergence. Experimental testing on standard MCNC benchmark circuits demonstrated that our optimized GA secures a 4.8% reduction in dead space compared to classical simulated annealing approaches. The average total wirelength was minimized by 11.2%, while the algorithm execution time remained stable under 65 s for complex blocks. This provides integrated circuit engineers with a balanced, automated tool for early-stage physical layout synthesis.

Keywords: VLSI Floorplanning, Genetic Algorithms, Multi-Objective Optimization, Physical Design Automation, Slicing Trees

Manuscript Timeline: Received: December 01, 2003; Revised: January 18, 2004; Accepted: February 10, 2004; Published: March 08, 2004

Citation: Rostova, E., & Mendez, C. (2004). A Specialized Genetic Algorithm for the Multi-Objective Structural Optimization of VLSI Floorplanning. International Journal of Computer Science and Technology, 6(3), 17–24.