International Journal of Computer Science and Technology

International Journal of Computer Science and Technology Vol. 4, No. 7, July 2002 | pp. 49–56

DOI: 10.46882/2002/IJCST/000043

Research Article

Title: A Multilevel Directory Cache Consistency Scheme for High-Density Processing Arrays

Names of Authors: Arthur Pendelton¹, Yuki Sato²

Authors’ Affiliations: ¹Department of Computer Architecture, University of Texas at Austin, USA; ²Graduate School of Engineering, Osaka University, Osaka, Japan.

Abstract:
Modern multi-processor systems face critical scalability and latency barriers when maintaining memory consistency across highly parallel compute environments. Standard directory-based cache coherence protocols induce extreme network message overheads and memory lookup bottlenecks as core counts expand. This paper develops an optimized, multi-level directory cache coherence protocol designed specifically for high-density, shared-memory processing arrays. The proposed protocol partitions directory records into localized clusters and uses a predictive sharing filter to restrict speculative coherence messages across the global interconnect bus. We evaluated our architectural engine using a cycle-accurate hardware simulator configured with up to 64 parallel processing cores executing diverse computational kernels. The experimental results show a 28.5% reduction in total cache-coherence message traffic and a 16.4% improvement in application execution speed relative to traditional MESI and MOESI baseline setups. The directory tracking memory footprint was lowered by 22.3%, ensuring that hardware scalability constraints are handled without imposing massive silicon area overheads within next-generation symmetric multiprocessing chips.

Keywords: Cache Coherence, Shared Memory, Parallel Architectures, Hardware Simulator, Multiprocessor Systems, Scalable Memory.

Manuscript Timeline: Received: March 02, 2002; Revised: April 08, 2002; Accepted: May 02, 2002; Published: July 18, 2002.

Citation: Pendelton, A., & Sato, Y. (2002). A Multilevel Directory Cache Consistency Scheme for High-Density Processing Arrays. International Journal of Computer Science and Technology, 4(7), 49–56.

International Journal of Computer Science and Technology Vol. 4, No. 7, July 2002 | pp. 49–56

DOI: 10.46882/2002/IJCST/000043

Research Article

Title: A Multilevel Directory Cache Consistency Scheme for High-Density Processing Arrays

Names of Authors: Arthur Pendelton¹, Yuki Sato²

Authors’ Affiliations: ¹Department of Computer Architecture, University of Texas at Austin, USA; ²Graduate School of Engineering, Osaka University, Osaka, Japan.

Abstract:
Modern multi-processor systems face critical scalability and latency barriers when maintaining memory consistency across highly parallel compute environments. Standard directory-based cache coherence protocols induce extreme network message overheads and memory lookup bottlenecks as core counts expand. This paper develops an optimized, multi-level directory cache coherence protocol designed specifically for high-density, shared-memory processing arrays. The proposed protocol partitions directory records into localized clusters and uses a predictive sharing filter to restrict speculative coherence messages across the global interconnect bus. We evaluated our architectural engine using a cycle-accurate hardware simulator configured with up to 64 parallel processing cores executing diverse computational kernels. The experimental results show a 28.5% reduction in total cache-coherence message traffic and a 16.4% improvement in application execution speed relative to traditional MESI and MOESI baseline setups. The directory tracking memory footprint was lowered by 22.3%, ensuring that hardware scalability constraints are handled without imposing massive silicon area overheads within next-generation symmetric multiprocessing chips.

Keywords: Cache Coherence, Shared Memory, Parallel Architectures, Hardware Simulator, Multiprocessor Systems, Scalable Memory.

Manuscript Timeline: Received: March 02, 2002; Revised: April 08, 2002; Accepted: May 02, 2002; Published: July 18, 2002.

Citation: Pendelton, A., & Sato, Y. (2002). A Multilevel Directory Cache Consistency Scheme for High-Density Processing Arrays. International Journal of Computer Science and Technology, 4(7), 49–56.

International Journal of Computer Science and Technology Vol. 4, No. 5, May 2002 | pp. 33–40

DOI: 10.46882/2002/IJCST/000041

Research Article

Title: A Structural Dependency Mapping Model for Relational Hierarchy Transformations

Names of Authors: Robert K. Jones¹, Amara Okafor²

Authors’ Affiliations: ¹Department of Software Engineering, Australian National University, Canberra, Australia; ²Department of Computer Science, University of Ibadan, Ibadan, Nigeria.

Abstract:
Enterprise computing centers face significant interoperability and data-loss challenges when migrating legacy records into modern object-oriented database management architectures. Structural differences between traditional tabular records and hierarchical object classes often cause runtime exceptions, broken relational linkages, and slow querying speeds. This paper introduces a formal, automated schema transformation model designed to map entity-relationship structures into optimized object-oriented formats smoothly. The framework uses a structural dependency mapping engine that evaluates table constraints, foreign key mappings, and cardinality indices before constructing equivalent class inheritance trees. We tested the execution efficiency of our migration engine by transferring an enterprise resource planning database containing 50 million records and 400 interconnected tables. The system completed the complete structural transformation process without requiring human repair scripts, achieving 100% data integrity preservation. Post-migration query benchmarks show a 31.4% improvement in complex data retrieval operations, validating that our object nesting logic successfully avoids high-overhead join statements in production environments.

Keywords: Database Migration, Schema Transformation, Object-Oriented Databases, Data Integrity, Relational Mapping, Enterprise Software.

Manuscript Timeline: Received: January 08, 2002; Revised: February 18, 2002; Accepted: March 11, 2002; Published: May 22, 2002.

Citation: Jones, R. K., & Okafor, A. (2002). A Structural Dependency Mapping Model for Relational Hierarchy Transformations. International Journal of Computer Science and Technology, 4(5), 33–40.

International Journal of Computer Science and Technology Vol. 4, No. 4, April 2002 | pp. 25–32

DOI: 10.46882/2002/IJCST/000040

Research Article

Title: An Adaptive Flow Threshold Control Mechanism for Network Packet Shifting

Names of Authors: Marcus Vance¹, Nadia Al-Suwaidi²

Authors’ Affiliations: ¹School of Computer Science, McGill University, Montreal, Canada; ²Department of Computer Engineering, United Arab Emirates University, Al Ain, UAE.

Abstract:
Packet-switched communication routers encounter massive packet drop rates and elevated queuing delays during heavy network traffic bursts, severely degrading the Quality of Service (QoS) for real-time media streams. Static buffer allocation policies either fail to capture sudden transmission surges or cause excessive packet delays due to bloated queue architectures. This paper introduces an optimized, dynamic buffer management algorithm that automatically calibrates queue thresholds based on real-time packet arrival rates and port utilization metrics. The framework applies a mathematical threshold adjustments scheme that penalizes non-responsive flows while prioritizing time-critical multimedia packets. We simulated our dynamic buffer configuration using a multi-node network simulator operating under a heavy mix of TCP and UDP data packets. The experimental outcomes indicate a 26.3% reduction in overall packet drop rates and a 38-millisecond improvement in average end-to-end queuing latency compared to standard Random Early Detection and Drop-Tail routing approaches. The system maintains uniform channel utilization across heavily congested backbone switches without inducing packet reordering anomalies, proving its efficacy for high-speed network infrastructures.

Keywords: Buffer Management, Quality of Service, Network Congestion, Packet Switching, Queue Optimization, Router Performance.

Manuscript Timeline: Received: December 01, 2001; Revised: January 10, 2002; Accepted: February 02, 2002; Published: April 15, 2002.

Citation: Vance, M., & Al-Suwaidi, N. (2002). An Adaptive Flow Threshold Control Mechanism for Network Packet Shifting. International Journal of Computer Science and Technology, 4(4), 25–32.

International Journal of Computer Science and Technology Vol. 4, No. 3, March 2002 | pp. 17–24

DOI: 10.46882/2002/IJCST/000039

Review Article

Title: A Performance Analysis of Takagi-Sugeno Inference Architectures in Manufacturing Pipelines

Names of Authors: Jean-Pierre Dubois¹, Sanjay Mehta²

Authors’ Affiliations: ¹Institute of Automation, École Polytechnique Fédérale de Lausanne, Switzerland; ²Department of Electrical Engineering, Indian Institute of Technology, Bombay, India.

Abstract:
The application of classical linear control theory to complex industrial production systems often yields poor performance due to non-linearities, unmodeled dynamics, and unpredictable load disturbances. Fuzzy logic controllers have emerged as a resilient alternative, bridging human expert heuristic rules with computational execution loops. This paper presents a comprehensive methodological survey analyzing the design, implementation, and long-term stability parameters of fuzzy expert systems across diverse manufacturing plants. We synthesize empirical data from 92 foundational studies published across the past decade, contrasting Mamdani and Takagi-Sugeno inference models applied to chemical, metallurgical, and automotive assembly pipelines. The survey assesses criteria such as rule-base optimization, membership function tuning, computational runtime overhead, and fault tolerance boundaries under extreme environmental noise. The review reveals that while Takagi-Sugeno configurations consistently deliver superior mathematical precision in tracking high-speed mechanical trajectories, Mamdani architectures offer unmatched transparency and simpler debugging workflows for human operators. We summarize current barriers including rule-base explosion in multi-variable configurations and lack of formal mathematical proof structures for absolute stability, concluding with a standardized design template for hybrid fuzzy-proportional-integral-derivative (Fuzzy-PID) control systems.

Keywords: Fuzzy Logic Controllers, Industrial Automation, Process Engineering, Expert Systems, Rule Optimization, Comparative Review.

Manuscript Timeline: Received: November 12, 2001; Revised: December 20, 2001; Accepted: January 14, 2002; Published: March 25, 2002.

Citation: Dubois, J. P., & Mehta, S. (2002). A Performance Analysis of Takagi-Sugeno Inference Architectures in Manufacturing Pipelines. International Journal of Computer Science and Technology, 4(3), 17–24.

International Journal of Computer Science and Technology Vol. 3, No. 11, November 2001 | pp. 81–88

DOI: 10.46882/2001/IJCST/000035

Research Article

Title: An Iterative Vertex Partitioning Architecture for Complex Structural Schemas

Names of Authors: Sarah Jenkins¹, Vikram Rao²

Authors’ Affiliations: ¹Department of Computer Science, Columbia University, New York, USA; ²School of Computer Science and Automation, Indian Institute of Science, Bangalore, India.

Abstract:
Distributed graph storage architectures experience notable data congestion when running multi-hop traversal actions across heavily connected relational schemas. The main technical challenge stems from distributing dense node topologies across multiple database servers without creating extensive cross-partition edge separations that increase cross-network transmission overhead. This study presents a dynamic multi-level graph sorting model, Balanced Vertex-Cut (BVC), engineered to manage power-law link distributions. The system balances individual vertex operations while simultaneously reducing data replication rates across separate cluster locations. We built the BVC partitioning system into a multi-node distributed configuration and analyzed query timelines against a synthetic relational chart containing 100 million vertices and 1.5 billion links. The empirical results prove that the BVC model cuts inter-node network data transmissions by 41.2% and accelerates long-path tracking actions by a factor of 3.5 relative to standard random sorting configurations. Storage volume variance remained within 2.1%, showing solid allocation balancing even during massive data additions.

Keywords: Graph Partitions, Network Topologies, Distributed Databases, Structural Analytics, Data Scaling, Database Optimization.

Manuscript Timeline: Received: July 15, 2001; Revised: August 25, 2001; Accepted: September 14, 2001; Published: November 28, 2001.

Citation: Jenkins, S., & Rao, V. (2001). An Iterative Vertex Partitioning Architecture for Complex Structural Schemas. International Journal of Computer Science and Technology, 1(11), 81–88.